MOS resistance controlling device and MOS attenuator

ABSTRACT

A MOS resistance controlling device includes: a plurality of MOS transistors having a first MOS transistor to N-th (the integer N is larger than 1) MOS transistor being serially connected, the source of the first MOS transistor being set to a first reference potential, the drain the N-th MOS transistor being set to a second reference potential, and the drain of an I-th MOS transistor being connected to the source of an I+1-th MOS transistor, where I is an integer from 1 to N−1; a current source which is electrically disposed at connection node between the drain of the N-th MOS transistors and the second reference potential; and an operational amplifier having a first input terminal being supplied with a third reference potential, a second input terminal connected with the connection node and an output terminal being connected with gates of the MOS transistors.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromthe prior Japanese Patent Application No. 2006-303775, filed on Nov. 9,2006; the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a MOS resistance controlling device forcontrolling the resistance between the source and drain of a MOStransistor and a MOS attenuator having the MOS resistance controllingdevice.

2. Description of the Related Art

A MOS transistor is widely available as a resistance element for variouselectronic circuits. In this case, the linear region of the MOStransistor is utilized. In the linear region of the MOS transistor, theresistance “Rmos” between the drain and source of the MOS transistor canbe approximately represented by the equation of Rmos≈1/{β·(Vgs−Vth)}.Herein, β=(μn·Cox)·(W/L) (μn: electron mobility, Cox: gate oxidecapacitance per unit area, L: gate length of MOS transistor, W: gatewidth of MOS transistor, Vgs: voltage between gate and source of MOStransistor, Vth: threshold voltage). Therefore, the resistance “Rmos”can be varied by changing the gate voltage Vgs.

A MOS resistance controlling circuit is exemplified in Reference 1, anduses a feedback circuit with an operational amplifier. Schematically,the gate voltage to realize the intended MOS resistance is obtainedthrough the feedback of the voltage between the source and drain of theMOS transistor to the operational amplifier. In this case, the gatevoltage is applied to the gate of another MOS transistor so that anotherMOS transistor is controlled so as to have the intended MOS resistance.

A variable attenuator is disclosed in Reference 2 as an applicationcircuit using the MOS resistance. Schematically, the MOS resistances areemployed as a ground resistance and a passing resistance, respectivelyand the gate voltage of the MOS transistor to ground is varied so as torealize the variable attenuator. Since the characteristic impedance ofthe attenuator is shifted from a predetermined value (renderednon-matching state) if only the ground resistance is changed, aprescribed voltage is applied to the gate of the passing MOS transistorso that the characteristic impedance of the attenuator is set to thepredetermined value. In order to obtain the predetermined voltage, adummy circuit (replica) with a circuit structure similar to the one ofthe variable attenuator and a feedback circuit with an operationalamplifier are provided.

The voltage generated according to Reference 1 can be supplied to thegate of the ground MOS transistor. In this case, even though thecharacteristics (e.g., threshold voltages) of the ground MOS transistorand the MOS transistor to supply the gate voltage are shifted similarly,the attenuation can be controlled precisely by the combination of theMOS transistors. However, if the operational amplifier in thecontrolling circuit of the MOS resistance has a DC offset, the variableattenuator is affected by the DC offset of the operational amplifier.References 1 and 2 do not teach the means for mitigating theabove-described problem.

-   -   [Reference 1] JP-A 10-200334 (KOKAI)    -   [Reference 2] Hakan Dogan, Robert G. Meyer and Ali M. Niknejad        BWRC, UC Berkeley, “A DC-10 GHZ Linear-in-dB Attenuator in 0.13        μm CMOS Technology”, IEEE 2004 CUSTOM INTEGCONSTANT CIRCUITS        CONFERENCE pp 609 to 612

BRIEF SUMMARY OF THE INVENTION

It is an object of the present invention to provide a MOS resistancecontrolling device to enhance the precision in control of the MOSresistance and a MOS attenuator having the MOS resistance controllingdevice.

In order to achieve the above object, an aspect of the present inventionrelates to a MOS resistance controlling device, including: a pluralityof MOS transistors having a first MOS transistor to N-th (the integer Nis larger than 1) MOS transistor being serially connected, the source ofthe first MOS transistor being set to a first reference potential, thedrain the N-th MOS transistor being set to a second reference potential,and the drain of an I-th MOS transistor being connected to the source ofan I+1-th MOS transistor, where I is an integer from 1 to N−1; a currentsource which is electrically disposed at connection node between thedrain of the N-th MOS transistors and the second reference potential;and an operational amplifier having a first input terminal beingsupplied with a third reference potential, a second input terminalconnected with the connection node and an output terminal beingconnected with gates of the MOS transistors.

In the MOS resistance controlling device according to the aspect, aplurality of MOS transistors are connected in series with one anotherand the output terminal of the operational amplifier is connected withthe gates of the MOS transistors. Therefore, the input offset voltage ofthe operational amplifier is allotted to the MOS transistors,respectively so that the affection of the input offset voltage can bedispersed by the MOS transistors connected in series with one another.As a result, each MOS resistance of each MOS transistor can becontrolled precisely.

Another aspect of the present invention relates to a MOS attenuator,including: a plurality of MOS transistors which are connected in serieswith one another so that each source is connected with each drain and anoutermost source in the MOS transistors is set to a first referencepotential; a current source which is electrically disposed between anoutermost drain in the MOS transistors and a second reference potential;a first operational amplifier having a first input terminal, a secondinput terminal and an output terminal so that a third referencepotential is supplied to the first input terminal and the second inputterminal is connected with a connection node electrically disposedbetween the outermost drain and the second reference potential, and theoutput terminal is connected with gates of the MOS transistors; a firstattenuator having an input terminal, an output terminal, a plurality ofground MOS transistors and at least one passing MOS transistor, theground MOS transistors and the passing MOS transistor being disposedbetween the input terminal and the output terminal of the firstattenuator, so that the output terminal of the first operationalamplifier is connected with gates of the ground MOS transistors and acontrol voltage is supplied to a gate of the at least one passing MOStransistor so as to set a characteristic impedance between the inputterminal and the output terminal to a predetermined value; a firstresistor, electrically disposed between the input terminal of the firstattenuator and a fourth reference potential, having an impedancecorresponding to the characteristic impedance; a second resistor,electrically disposed between the output terminal of the firstattenuator and a fifth reference potential, having an impedancecorresponding to the characteristic impedance; a second operationalamplifier to generate an amplified output signal in comparison with avoltage at the output terminal of the first attenuator and apredetermined voltage and to output the amplified output signal as thecontrol voltage; and a second attenuator having an input terminal, anoutput terminal, a plurality of ground MOS transistors and at least onepassing MOS transistor, the ground MOS transistors and the passing MOStransistor being disposed between the input terminal and the outputterminal of the second attenuator, so that the output terminal of thefirst operational amplifier is connected with gates of the ground MOStransistors and the control voltage is supplied to a gate of the atleast one passing MOS transistor.

The MOS attenuator utilizes the MOS resistance controlling device asdescribed above. In this case, the output voltage of the MOS resistancecontrolling device is supplied so as to generate the MOS resistances ofthe ground MOS transistors in the attenuator. As a result, the MOSresistances of the ground MOS transistors can be controlled precisely sothat the attenuation of the attenuator can be controlled as designed.

According to the aspects of the present inventions, the controlprecision in MOS resistance of the MOS resistance controlling device andthe MOS attenuator can be enhanced.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

FIG. 1 is a circuit diagram relating to a MOS resistance controllingdevice according to an embodiment.

FIG. 2 is a characteristic view for explaining the operation of theembodiment shown in FIG. 1.

FIG. 3 is a circuit diagram for explaining the affection of the offsetof the operational amplifier in the embodiment shown in FIG. 1.

FIG. 4 is a characteristic view for explaining the operation of theembodiment shown in FIG. 1 in view of the affection of the offset of theoperational amplifier relating to FIG. 3.

FIG. 5 is a reference circuit diagram for the embodiment shown in FIG.1.

FIG. 6 is a characteristic view for explaining the operation of thecircuit shown in FIG. 5.

FIG. 7 is a circuit diagram relating to a MOS resistance controllingdevice according to another embodiment.

FIG. 8 is a circuit diagram relating to a MOS resistance controllingdevice according to still another embodiment.

FIG. 9 is a circuit diagram relating to a MOS resistance controllingdevice according to a further embodiment.

FIG. 10 is a circuit diagram relating to a MOS attenuator according toan embodiment.

FIG. 11 is a circuit diagram relating to a MOS attenuator according toanother embodiment.

DETAILED DESCRIPTION OF THE INVENTION

In an embodiment, the semiconductor area for a channel of each MOStransistor to be formed is electrically set to the first referencepotential. Generally, the MOS transistor includes a semiconductor area(e.g., semiconductor substrate) for the channel to be formed. Therefore,if the first reference potential is set to the semiconductor area, themanufacturing process of a semiconductor device including the MOStransistors and the chip area of the semiconductor device can bereduced.

In another embodiment, the semiconductor area for a channel of each MOStransistor to be formed is electrically set to a source potential ofeach MOS transistor. In this case, the semiconductor area for thechannel of each MOS transistor to be formed is set to the sourcepotential thereof so that the fluctuation in characteristic (e.g.,threshold value) between the MOS transistors due to the substrate effectcan be prevented and thus, the output voltage can be generated at theoutput terminal of the operational amplifier as designed.

In still another embodiment, the gate length and gate width of the MOStransistors are set equal to the gate length and gate width of at leastone selected from among the ground MOS transistors in the firstattenuator. In this case, since the attenuator can be structured in thesame manner as the MOS resistance controlling device in view of thestructure of MOS transistor, the error for the designed attenuationcharacteristic can be reduced.

In a further embodiment, the gate length of the MOS transistors are setequal to the gate length of at least one selected from among the groundMOS transistors in the first attenuator, and the gate width of the MOStransistors are set to a predetermined ratio for the gate width of atleast one selected from among the ground MOS transistors in the firstattenuator. In this case, if the gate width of the ground MOStransistors in the first attenuator is decreased, the current to beflowed in the MOS transistors can be reduced and thus, the electricpower saving can be realized.

The embodiments will be described with reference to drawings. FIG. 1 isa circuit diagram relating to a MOS resistance controlling deviceaccording to an embodiment. As shown in FIG. 1, the MOS resistancecontrolling device 10 includes MOS transistors 11, 12, an operationalamplifier 13, a constant current source 14 and a standard voltage source15. The output of the operational amplifier 13 corresponds to the outputVout of the MOS resistance controlling device 10.

The MOS transistors 11 and 12 are n-channel MOS transistors so that thesource of the MOS transistor 11 is connected in series with the drain ofthe MOS transistor 12 and the source of the MOS transistor 12 iselectrically grounded (first reference potential). Then, in the MOStransistors 11 and 12, the semiconductor areas (in the correspondingsemiconductor substrates) for the channels of the MOS transistors 11 and12 to be formed are electrically grounded, as depicted in FIG. 1. Then,the drain of the MOS transistor 11 is connected with one end of theconstant current source 14. A common output voltage is applied to thegates of the MOS transistors 11 and 12 from the operational amplifier13.

The operational amplifier 13 includes two input terminal and an outputterminal so that the voltage of the standard voltage source 15 (thirdreference potential) is supplied as an inverting input to one of theinput terminals of the operational amplifier 13 and the voltagegenerated at the connection node between the MOS transistor 11 and theconstant current source 14 is supplied as a non-inverting input to theother of the input terminals of the operational amplifier 13. The outputterminal of the operational amplifier 13 is connected with the gates ofthe MOS transistors 11 and 12. The constant current source 14 isdisposed between the drain of the MOS transistor 11 and the Vdd (secondreference potential) so that the current Icnt can be flowed in the MOStransistor 11. The standard voltage source 15 generates a referencepotential of 2Vref at the ends of the MOS transistors 11 and 12. Sincethe one of the input terminals is shorted imaginarily for the other ofthe input terminals, a voltage corresponding to the reference potentialof 2Vref is generated at the ends of the MOS transistors 11 and 12.

FIG. 2 is a characteristic view for explaining the operation of the MOSresistance controlling device shown in FIG. 1. The abscissa axisdesignates the source/drain voltage Vds of the MOS transistor 11 or 12and the ordinate axis designates the drain current Ids of the MOStransistor 11 or 12. When the gate/source voltage Vgs of the MOStransistor 11 or 12 is changed, the MOS resistance Rmos=Vds/Ids of theMOS transistor 11 or 12 is also changed (the relation between thesource/drain voltage Vds and the drain current Ids becomes linear in thevicinity of the original point. Referring to the circuit diagram shownin FIG. 1, the MOS resistance Rmos can be represented by “Vref/Icnt”.Therefore, the Vref and Icnt can be defined as a given point of the linedepicted in FIG. 2.

Strictly, since the gate/source voltage Vgs of the MOS transistor 11 isdifferent from the gate/source voltage Vgs of the MOS transistor 12, thesource/drain voltage Vds of the MOS transistor 11 is also different fromthe source/drain voltage Vds of the MOS transistor 12. If the differencein gate/source voltage Vgs between the MOS transistors 11 and 12 issmall (substantially equal to one another), the source/drain voltage Vdsof the MOS transistor 11 becomes almost equal to the source/drainvoltage Vds of the MOS transistor 12 (in this case, the source/drainvoltage Vds can be represented by “Vref”).

The output voltage of the operational amplifier 13 which is supplied asthe gate voltage of the MOS transistor 12 is a voltage to generate thesame MOS resistance in another MOS transistor to be connected with theoutput terminal 16 as the MOS resistance in the MOS transistor 12. Inthis case, the size (gate length and gate width) of another MOStransistor is set equal to the size of the MOS transistor 12. In thecase that the gate length of another MOS transistor is set equal to thegate length of the MOS transistor 12, if the gate width of the anotherMOS transistor is set larger than the gate width of the MOS transistor12, the MOS resistance of another MOS transistor becomes larger than theMOS resistance of the MOS transistor 12. In other words, when the gatelength of another MOS transistor is set equal to the gate length of theMOS transistor 12, the MOS resistance of another MOS transistor isshifted from the MOS resistance of the MOS transistor 12 dependent onthe difference in gate width between another MOS transistor and the MOStransistor 12.

FIG. 3 is a circuit diagram for explaining the affection of the offsetof the operational amplifier in the MOS resistance controlling deviceshown in FIG. 1. As shown in FIG. 3, the DC offset Voff of theoperational amplifier 13 can be considered to be added to the inputterminal of the operational amplifier 13 as an electric power source 31.In this case, the source/drain voltages of the MOS transistors 11 and 12are set to “Vref+Voff/2”, respectively. Namely, the half of the DCoffset Voff of the operational amplifier 13 is allotted to the MOStransistors hand 12, respectively so that the MOS transistors 11 and 12are affected equally by the DC offset Voff of the operational amplifier13.

FIG. 4 is a characteristic view for explaining the operation of the MOSresistance controlling device shown in FIG. 1 in view of the affectionof the offset of the operational amplifier relating to FIG. 3. As shownin FIG. 3, since the source/drain voltage Vds is shifted from “Vref” to“Vref+Voff/2” in the MOS transistors 11 and 12, the MOS resistance Rmosis also shifted from “Vref/Icnt” to “(Vref+Voff/2)/Icnt” in the MOStransistors 11 and 12.

FIG. 5 is a reference circuit diagram for the MOS resistance controllingdevice shown in FIG. 1. Like or corresponding components are designatedby the same reference numerals throughout the drawings. In the MOSresistance controlling device 50, the MOS transistor 11 is not connectedin series with the MOS transistor 12 and the standard voltage Vref issupplied as the inverting input to the input terminal of the operationalamplifier 13 from the standard voltage source 15A.

FIG. 6 is a characteristic view for explaining the operation of thecircuit shown in FIG. 5. As shown in FIG. 6, since the source/drainvoltage Vds of the MOS transistor 12 is shifted to “Vref+Voff”, the MOSresistance Rmos of the MOS transistor 12 is also shifted to“(Vref+Voff/2)/Icnt”. In comparison with the MOS transistor 12 in FIG.3, the MOS transistor 12 in FIG. 5 is largely affected by the DC offsetVoff of the operational amplifier 13 (twice affected). Therefore, theMOS resistance of another MOS transistor to be connected with the outputterminal 16 is largely shifted from the intended MOS resistance. As aresult, the MOS resistance of another MOS transistor to be connectedwith the output terminal 16 in FIG. 3(FIG. 1) can be controlled moreprecisely than the MOS resistance of another MOS transistor in FIG. 5.

FIG. 7 is a circuit diagram relating to a MOS resistance controllingdevice according to another embodiment. Like or corresponding componentsare designated by the same reference numerals throughout the drawings,and not explained.

In this embodiment, a MOS transistor 71 is connected in series with theMOS transistors 11 and 12. The output voltage of the operationalamplifier 13 is supplied to the gate of the MOS transistor 71. Then, theoutput voltage of 3Vref is supplied as a reference potential to theinverting input terminal of the operational amplifier 13.

In this case, the source/drain voltages of the MOS transistors 71, 11and 12 are set to “Vref”, respectively so that the offset voltage of theoperational amplifier 13 is also allotted equally to the MOS transistors71, 11 and 12. Therefore, the MOS resistance of the MOS transistor 12can be generated under the condition of small affection of the offsetvoltage. If the number of MOS transistor to be connected in series isincreased, the affection of the offset voltage can be much reduced.

FIG. 8 is a circuit diagram relating to a MOS resistance controllingdevice according to still another embodiment. Like or correspondingcomponents are designated by the same reference numerals throughout thedrawings, and not explained.

In this embodiment, the MOS transistors 11A and 12A are provided insteadof the MOS transistors 11 and 12 as shown in FIG. 1. In this embodiment,the semiconductor areas (in the corresponding semiconductor substrates)for the channels of the MOS transistors 11A and 12A to be formed are setto the corresponding source potentials so that the substrate effect canbe prevented and thus, the circuit design can be simplified. Thesubstrate effect means the change in threshold voltage of a MOStransistor by the difference between the substrate voltage and thesource voltage.

FIG. 9 is a circuit diagram relating to a MOS resistance controllingdevice according to a further embodiment. Like or correspondingcomponents are designated by the same reference numerals throughout thedrawings, and not explained.

In the MOS resistance controlling device 90, a resistance 91 and astandard current source 92 to flow a current Iref in the resistance 91are provided instead of the standard voltage source 15. Other componentsare provided in the same manner as in FIG. 1. In this case, if thecurrent Iref and the current Icnt can be flowed in relation to oneanother from the standard current source 92 and the constant currentsource 14, respectively, the intended output voltage with small errorcan be generated at the output terminal 16.

FIG. 10 is a circuit diagram relating to a MOS attenuator according toan embodiment. Like or corresponding components are designated by thesame reference numerals throughout the drawings, and not explained.

In this embodiment, the MOS attenuator utilizes the MOS resistancecontrolling device 90 shown in FIG. 9. Therefore, the attenuation of theMOS attenuator can be varied by changing the current Iref of thestandard current source 92. The MOS attenuator includes a dummy(replica) attenuator 101 containing MOS transistors and a realattenuator 103 for passing signals containing MOS transistors inaddition to the MOS resistance controlling device 90.

With the dummy attenuator 101, a resistance R0 corresponding to theimpedance of a signal source is connected to the input terminal thereof.The one end of the resistance R0 is electrically grounded. Then, aresistance R1 corresponding to the terminating resistance is connectedto the output terminal thereof. The one end of the resistance R1 iselectrically connected to the Vdd. In the dummy attenuator 101, groundMOS transistors T1, T2, T3 and passing MOS transistors T4, T5 areprovided. The output voltage of the MOS resistance controlling device 90is supplied to the gates of the MOS transistors T1, T2, T3,respectively. Then, the output of the operational amplifier 102 issupplied to the gates of the MOS transistors T4, T5 so that thecharacteristic impedance of the dummy attenuator 101 can be set to apredetermined value.

The real attenuator 103 is structured in the same manner as the dummyattenuator 101. The resistances R4, R5, R6, R7 and R8, which areconnected to the gates of the MOS transistors T6, T7, T8, T9 and T10,respectively, reduce high frequency signals input into the attenuator103. Therefore, the high frequency signals can be reduced remarkablythrough the attenuator 103. Then, the output voltage of the MOSresistance controlling device 90 is supplied to the gates of the MOStransistors T6, T7, T8. Moreover, the output of the operationalamplifier 102 is supplied to the gates of the MOS transistors T9, T10.

The output terminal of the dummy attenuator 101 is connected with theresistance R1 and the non-inverting input terminal of the operationamplifier 102. The voltage generated at the node between the resistancesR2 and R3 is supplied to the inverting input terminal of the operationalamplifier 102. In this case, since the input terminals of theoperational amplifier 102 are shorted imaginarily, the output of theoperational amplifier 102 is fed back to the dummy attenuator 101(concretely, to the gates of the MOS transistors T4, T5) so that theresistance R3 is provided imaginarily in the attenuator 101 when theresistance R1 is set equal to the resistance R2. Therefore, if theresistance R2 and R3 are set to a predetermined characteristicimpedance, the characteristic impedance of the attenuator 101 can be setto the predetermined characteristic impedance. In this case, thecharacteristic impedance of the attenuator 103 is also set to thepredetermined characteristic impedance.

In the MOS attenuator as shown in FIG. 10, the output voltage of the MOSresistance controlling device 90 is supplied to the gates of the MOStransistors T1, T2, T3, T6, T7, T8 in the attenuator 101 and 103.Therefore, the intended MOS resistance with small affection of theoffset voltage of the operational amplifier 13 can be generated at theMOS transistors T1, T2, T3, T6, T7, T8. The error for the designedattenuation characteristic can be reduced. In order to enhance thereduction of the error, it is desired that the MOS resistancecontrolling device 90 is provided in the vicinity of the attenuators 101and 103 so that the MOS transistors 11 and 12 in the device 90 can berelated with the MOS transistors T1, T2, T3, T6, T7, T8.

The MOS transistor T2 is shared with two sets of circuits in the dummyattenuator 101 and the MOS transistor T7 is shared with two sets of πcircuits in the real attenuator 103. Therefore, it is desired that theMOS resistance of the MOS transistor T2 and/or T7 is decreased half aslarge as the MOS resistance of the MOS transistors T1, T3 and/or T6, T8by increasing the size (gate width) of the MOS transistor T2 and/or T7twice as large as the sizes (gate widths) of the MOS transistors T1, T3and/or T6, T8. In this case, the current density in the MOS transistorT2 and/or T7 can be set equal to the current density in the MOStransistors T1, T3 and/or T6, T8.

Under the above-described condition, the sizes (gate widths) of the MOStransistors T1, T2, T3 in the dummy attenuator 101 may be set smallerthan the sizes (gate widths) of the MOS transistors 11 and 12 in the MOSresistance controlling device 90. In this case, since the currentflowing in the dummy attenuator 101 can be reduced, the electric powersaving can be realized for the attenuator 101 (that is, the MOSattenuator shown in FIG. 10). For simplifying the manufacturing process,it is desired that the gate lengths of the MOS transistors are set equalto one another irrespective of the gate widths thereof.

FIG. 11 is a circuit diagram relating to a MOS attenuator according toanother embodiment. In this embodiment, MOS transistors T11, T12, T21,T22, T31, T32 are provided in a dummy attenuator 101A instead of the MOStransistors T1, T2, T3 in the dummy attenuator 101. The MOS transistorsT11 and T12; T21 and T22; T31 and T32 are structured in the same manneras the MOS transistors 11 and 12 in the MOS resistance controllingdevice 90. The MOS transistors T11 and T12 are configured such that thesource of the MOS transistor T11 is connected in series with the drainof the MOS transistor T12 and the source of the MOS transistor T12 iselectrically grounded (first reference potential). The semiconductorareas (in the corresponding semiconductor substrates) for the channelsof the MOS transistors T11 to T32 to be formed are electricallygrounded, as depicted in FIG. 1.

In this embodiment, MOS transistors T61, T62, T71, T72, T81, T82 areprovided in a real attenuator 103A instead of the MOS transistors T6,T7, T8 in the real attenuator 103. The MOS transistors T61 and T62; T71and T72; T81 and T82 are structured in the same manner as the MOStransistors 11 and 12 in the MOS resistance controlling device 90. TheMOS transistors T61 and T62 are configured such that the source of theMOS transistor T61 is connected in series with the drain of the MOStransistor T62 and the source of the MOS transistor T62 is electricallygrounded (first reference potential). The semiconductor areas (in thecorresponding semiconductor substrates) for the channels of the MOStransistors T61 and T82 to be formed are electrically grounded, asdepicted in FIG. 1.

Although the present invention was described in detail with reference tothe above examples, this invention is not limited to the abovedisclosure and every kind of variation and modification maybe madewithout departing from the scope of the present invention. For example,some constituents in one embodiment may be combined with someconstituents in another embodiment. Moreover, some constituents in oneembodiment may be omitted appropriately.

1. A MOS attenuator, comprising: a plurality of MOS transistors having afirst MOS transistor to N-th (the integer N is larger than 1) MOStransistor being serially connected, the source of the first MOStransistor being set to a first reference potential, the drain of theN-th MOS transistor being set to a second reference potential, and thedrain of an I-th MOS transistor being connected to the source of anI+1-th MOS transistor, where I is an integer from 1 to N−1; a currentsource which is electrically disposed at a connection node between thedrain of the N-th MOS transistors and the second reference potential;and a first operational amplifier having a first input terminal, asecond input terminal and an output terminal, a third referencepotential being supplied to the first input terminal, and the secondinput terminal being connected with a connection node electricallydisposed between the drain of the N-th transistor and the secondreference potential, and the output terminal being connected with gatesof the MOS transistors; a first attenuator having an input terminal, anoutput terminal, a plurality of ground MOS transistors and at least onepassing MOS transistor, the ground MOS transistors and the passing MOStransistor being disposed between the input terminal and the outputterminal of the first attenuator, so that the output terminal of thefirst operational amplifier is connected with gates of the ground MOStransistors and a control voltage is supplied to a gate of the at leastone passing MOS transistor so as to set a characteristic impedancebetween the input terminal and the output terminal to a predeterminedvalue; a first resistor, electrically disposed between the inputterminal of the first attenuator and a fourth reference potential,having an impedance corresponding to the characteristic impedance; asecond resistor, electrically disposed between the output terminal ofthe first attenuator and a fifth reference potential, having animpedance corresponding to the characteristic impedance; a secondoperational amplifier to generate an amplified output signal incomparison with a voltage at the output terminal of the first attenuatorand a predetermined voltage and to output the amplified output signal asthe control voltage; and a second attenuator having an input terminal,an output terminal, a plurality of ground MOS transistors and at leastone passing MOS transistor, the ground MOS transistors and the passingMOS transistor being disposed between the input terminal and the outputterminal of the second attenuator, so that the output terminal of thefirst operational amplifier is connected with gates of the ground MOStransistors and the control voltage is supplied to a gate of the atleast one passing MOS transistor.
 2. The attenuator as set forth inclaim 1, wherein a gate length and gate width of the MOS transistors areset equal to a gate length and gate width of at least one selected fromamong the ground MOS transistors in the first attenuator.
 3. Theattenuator as set forth in claim 1, wherein a gate length of the MOStransistors are set equal to a gate length of at least one selected fromamong the ground MOS transistors in the first attenuator; wherein a gatewidth of the MOS transistors are set to a predetermined ratio for a gatewidth of at least one selected from among the ground MOS transistors inthe first attenuator.
 4. The attenuator as set forth in claim 1, whereina semiconductor area for a channel of each MOS transistor to be formedis electrically set to the first reference potential.
 5. The attenuatoras set forth in claim 1, wherein a semiconductor area for a channel ofeach MOS transistor to be formed is electrically set to a sourcepotential of each MOS transistor.
 6. The attenuator as set forth inclaim 1, wherein an electric potential of the first input terminal ofthe first operational amplifier is set equal to an electric potential ofthe second input terminal of the first operational amplifier.
 7. Theattenuator as set forth in claim 1, wherein an electric potential of thefirst input terminal of the second operational amplifier is set equal toan electric potential of the second input terminal of the secondoperational amplifier.
 8. The device as set forth in claim 6, whereinthe third reference potential is defined by a voltage from a standardvoltage source.
 9. The device as set forth in claim 6, wherein the thirdreference potential is defined by a resistance and a current from astandard current source to be flowed in the resistance.